A Wideband 6-bit Phase Shifter with Low RMS Error in 65nm CMOS Technology

This letter presents a wideband 6-bit phase shifter with low RMS error in 65nm CMOS technology. Compared with conventional cascode-cascade structure, this active balun utilizes cascode topology, current negative feedback, and symmetrical structure at the same time to minimize phase/amplitude difference and realize stable operation. The three-order RC-CR networks with different resonant frequency generate precise orthogonal signals to control vector adder. The current reference circuit used in DAC gives precise current reference and acts as negative feedback to stabilize the working operation. Digital-to-analog converter(DAC) uses cascode current mirror to copy precise current reference and compensate the phase/amplitude error in the wide band. The experimental result shows that RMS amplitude error and phase error are less than 0.7 dB and 3.2°, respectively, over the bandwidth. The measured return loss is observed better than 9dB from 2 to 18GHz. Its total consumption is 92.4mW under 3.3V supply voltage, and the core chip occupies $600 \mu \mathrm{m} \times 700 \mu \mathrm{m}$.