Architecture Analysis and Simulink Modeling of a High Resolution Zoom ADC

This paper analyzes the principle of the architecture and key circuit modules of a high resolution discrete Zoom Analog-to-Digital Converter (Zoom ADC) used in multicolor detectors, and uses Matlab Simulink to model in the behavior level and verifies its function and performance. Zoom ADC uses a front-end coarse 5-bit Asynchronous Successive Approximation Register Analog-to-Digital Converter (SAR ADC) to dynamically adjust the reference voltage of a back-end fine third order 2-bit Sigma-Delta modulator (SDM) to effectively improve the dynamic range of the system. An additional feedforward path combined with a 2-bit quantizer minimizes quantization noise in SAR ADC, and the Data Weighted Average (DWA) algorithm performs first order noise shaping for capacitor mismatches in 5-bit fine Capacitance Digital-to-Analog Converter (CDAC),and introduces the over-ranging factor M, which not only relaxes the quantization error of SAR ADC, but also effectively prevents SDM overload. Simulink modeling results show that the signal to noise distortion ratio (SNDR) of the output signal is greater than 117 dB and the effective bit (ENOB) is greater than 19 bits when the input signal frequency is within the bandwidth of 10 KHz, the oversampling rate is 128, and the signal amplitude is −0.9dBFS.