A 8 Channels 14 bits 100 MHz Sample and Hold Circuit Based on Delay-Locked Loop Control

In order to improve the sampling frequency and sampling accuracy of the analog-to-digital converter, a multichannel sample and hold circuit controlled by delay-locked loop was designed based on 40nm CMOS process. A low jitter and low power delay-locked loop with pseudo-differential delay unit was improved as the clock control input of the eight channels sample and hold circuit. In the case of not affecting the sampling precision of the sample and hold circuit, eight channels can be sampled in turn. The precision of the sample and hold circuit is 13.8 bits, the sampling frequency is 100 MHz, and the SFDR is 85 dB. The cascaded simulation of the circuit proved that the circuit can meet the precision requirements, and the structure has strong practicability.