High-Efficiency Digital Power Amplifier Design Based on 22-nm CMOS Process

In this paper, a digital power amplifier (DPA) with high power, high efficiency and six efficiency peak points is designed for polarized transmitter system based on 22-nm CMOS process. Power amplifier (PA) cells adopt the switched-capacitor PA (SCPA) structure. And the output port adopts a transformer-based four-in-one power combining network to achieve peak output power of more than 1 W. The power back-off (PBO) scheme using three efficiency-enhancement techniques, Class-G, Doherty and Time Interleaving (TI), produces six peak efficiency points. The simulated results show that the peak output power is 30.6 dBm at 2.4 GHz, and the drain efficiency are 52.7%, 51.1%, 52.0%, 46.6%, 39.6% and 23.5% at 0 dB, 2.5dB, 6 dB, 8.5 dB, 12 dB and 18 dB of power back-off. The DPA has the excellent amplitude modulation (AM)-AM distortion and the simulated AM-phase modulation (PM) distortion is less than 13°.