A 9 b 4 GS/s Time-Domain ADC with Self-Reset VTC and Switched-RO TDC Including 8x Hybrid Interpolation

This paper presents a 4-way time-interleaved 9-bit, 4-GS/s time-domain ADC, in which the TDC is realized by a switched RO with 4x conventional interpolation and extra 2x interpolation provided by a 2-threshold detector which halves the amount of interpolation cells. A memoryless self-reset voltage-to-time converter (VTC) with adaptive VCM generator is proposed to suppress the nonlinearity of conventional VTC. An off-chip synchronization algorithm is employed to avoid possible conversion error caused by the mismatch between the fine and coarse TDC. Fabricated in 65-nm CMOS and measured under 4 GS/s, the ADC achieves SFDR/SNDR of 60.4 dB/43.3 dB (for low input) and 54.2 dB/42.1 dB (for Nyquist input), respectively. The ADC including an on-chip input buffer consumes 176 mW power.