An 800MS/s 100MHz BW Continuous-Time Pipeline ADC with Integrator-filter and Digital Reconstruction Algorithm

This paper presents a two-stage continuous-time pipeline ADC with inherent anti-aliasing using Integrator-filter and digital reconstruction algorithm without dither injection. The proposed Integrator-filter exhibits better performance compared with the first-order and second-order low-pass filters, allowing larger inter-stage gain and dynamic range. Also, an algorithm without dither injection is presented to obtain the tap weights of the reconstruction filters. The presented ADC clocked at 800MHz achieves 79.4dB peak SNDR with 100MHz bandwidth in 65-nm CMOS and consumes 14.7 mW, resulting in a FOM
s
of 177.7dB.