Small Footprint 6T-SRAM Design with MIV-Transistor Utilization in M3D-IC Technology

Metal inter-layer via (MIV) provides interconnects between sequentially grown substrate layers in monolithic three-dimensional integrated circuit (M3D-IC) technology. MIV with substrate around it forms a metal-insulator-semiconductor (MIS) structure, thus potentially interfering with devices around it. This paper studies the impact of the MIV on the characteristics of the nearby transistor, specifically the leakage current. Simulation results suggest that due to the internal placement of MIV, the leakage current increases by up to 528× compared with the transistor without internal MIV, for the assumed M3D-IC process. We then discuss the 6T-SRAM implementation in M3DIC technology without using internal MIVs as they significantly increase leakage. A compact SRAM cell by taking advantage of MIS structure is proposed in the paper. With this approach, the footprint is reduced by 19% compared with the conventional SRAM design in 2-layer transistor-level M3D implementation. In addition, the performance metrics of SRAM cell specifically hold margin, read margin, write margin, average read power, and average write power greatly improved for the proposed two-layer transistor-level SRAM design compared with the conventional two-layer transistor-level implementation.