Hardware Acceleration and Implementation of Fully Homomorphic Encryption Over the Torus

Fully Homomorphic Encryption (FHE) allows direct computation on ciphertext without decryption which provides an effectual approach for privacy-preserving computation. Bootstrapping is an useful feature to have in FHE scheme. However, limited by substantial memory requirements and costly computations, it is difficult to put bootstrapping into practice. It’s necessary to implement hardware acceleration for bootstrapping. In this paper, we proposed the first FPGA implementation of TFHE bootstrapping with 128-bit security to our acknowledgement. We designed a fixed distribution access pattern to accelerate polynomial multiplication and the simplified modular reduction circuit is designed to optimize the computations. The high-level pipelines are utilized to reduce the clock cycle consumption. We proposed multiple parallelism-matching architecture to further speed up the bootstrapping procedure. We implement entire bootstrapping scheme with various key unrolling factors on FPGA platform and synthesis an individual computational core in TSMC 28nm for performance evaluation. The experimental results indicate that our bootstrapping scheme can achieve
$5.5\times -34 \times $
speed up compared with the state-of-art CPU baselines. Compared with previous FPGA design, our acceleration achieves a latency improvement of
$6\%-65\%$
with higher security.