Hardware-Efficient Digital Autotuning for Integrated Switched-Mode Battery Chargers

Parameter variations and unpredictable operating environments heavily impact the control performance of battery chargers in mobile device applications. To address this challenge, a comprehensive and simple autotuning system has been developed. The autotuning algorithm presented in this work aims to maximize the crossover frequency of the control loop while maintaining stability margins. The key innovations behind this approach are the use of a single-tone injection, single-node measurement, and the decomposition of the response signal into in-phase and quadrature projections. This autotuning approach results in significant savings in computational hardware resources, as it requires virtually no memory and has a low number of signal processing components. The effectiveness of the algorithm has been experimentally verified on a field-programmable gate array (FPGA)-based controller and demonstrated on an integrated battery charger prototype. The proposed autotuning algorithm is only 73% larger than the standard proportional–integral control system and consumes just 3.2% resources of the FPGA chip (Cyclone V with 15 880 adaptive logic modules).