Design of High Speed BCD Adder Using CMOS Technology

Decimal arithmetic gains its importance in different applications in the fields of finance and scientific applications. The approach of running decimal arithmetic over binary hardware requires conversions from decimal to binary and from binary to decimal. These conversions produce inexact results that impose financial losses for companies. Therefore, the need for decimal hardware is of high importance. This work proposes decimal addition circuits and presents their realization in complementary metal-oxide semiconductor (CMOS) technology. LTSPICE SPICE simulator software is used to simulate and verify the functionality of the proposed circuits. The circuits are simulated using $45nm$ , $65nm$ , and $180nm$ technologies and compared against existing works in the literature. Due to the lack of existing work in literature and for purpose of comparison, this work also designed five different BCD adders using different existing binary adders in literature. The experimental results show that proposed decimal adder achieves better performance comparing to the other works. For example, for 3-digit operands, the proposed adder shows a power delay product (PDP), in femtojoule (fJ), of $13.88~fJ$ comparing to $25.38~fJ$ , $16.01~fJ$ , $15.24~fJ$ , $27.49~fJ$ , and $27.77~fJ$ PDP for other works.