Performance Evaluation of Novel Ternary Subtractor Circuits using Double Pass Transistor Logic

This paper proposes a novel circuit design of two Ternary Half Subtractor (THS) and a Ternary Full Subtractor (TFS) using Double pass transistor logic (DPL). The proposed THS is implemented by using basic ternary inverters and DPL implementation of Difference and Borrow circuits. The proposed TFS uses two 1:3 ternary decoder and two 3:1 ternary multiplexers and DPL implementation of Difference and Borrow circuits. This approach focuses on achieving low power consumption and propagation delay. The proposed TFS and THS circuits are compared with existing circuits and demonstrate superior performance based on their performance metrics. The circuit analysis and simulations were conducted using Cadence Virtuoso simulation software. Performance evaluation concludes that the proposed designs perform better than other circuits in terms of transistor count, latency and power-delay product (PDP), and hence are appropriate for high-performance Ternary computational circuits.