A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM

The remote-radio-head transceivers have started digitalizing radio frequency technology, thanks to its unparalleled bandwidth and flexibility, by employing giga-samples-per-second data converters [1]. Direct synthesizing and sampling of these converters must demand excellent phase noise (PN) performance, namely, the simultaneous realization of low spur and low jitter. Sub-sampling phase-locked loop (SS-PLL) is the most promising candidate to realize this target under low-power consumption due to high phase-detection gain [2], as shown in Fig. 1(top). Yet, the periodically sub-sampling operation induces several non-idealities, e.g., binary-frequency-shift-keying (BFSK) effect, charge sharing, and clock feedthrough, seriously deteriorating the reference spur. In [2] and [3], placing an isolated buffer between the voltage-controlled oscillator (VCO) and the sub-sampling phase detector (SS-PD) can effectively alleviate the above issues, but the high-frequency buffer consumes extra power and adds noise contribution. Interestingly, the isolated SS-PDs (iSS-PDs) have been devised to improve spur and save power simultaneously [4], [5]. Yet, as the VCO frequency increases, the transistor size of the iSS-PD becomes a remarkable consideration, as illustrated in Fig. 1(bottom). The large size of isolated NMOS (Ms) and sampling switches can ensure enough iSS-PD gain to suppress the in-band noise, but the large parasitic capacitance of Ms will seriously degrade the reference spur. On the other hand, the small size of the iSS-PD is beneficial to enhance the isolation for the improved reference spur, but it is hard to lower the in-band noise due to the undersized iSS-PD gain.