Complex Design of CMOS Logic With Tolerance to Particle and Cumulative Radiation

Silicon-based electronic components exposed to the radiation environment experience transient and cumulative damage, which causes performance degradation, malfunction, and burnout of the entire electronic system. In this study, the silicon-on-insulator (SOI) process technology was applied to enhance the single event effect (SEE) tolerance of bulk complementary metal–oxide–semiconductor (CMOS)-based logic circuits, which are vulnerable to space particle radiation. SOI CMOS processes are susceptible to total ionizing dose (TID) effects because of an additional oxide layer. A layout-modification technique (LMT) was proposed to overcome this problem. The SEE tolerance characteristics of the SOI process logic were verified in advance using radiation response modeling and simulation. The proposed radiation-hardened (RH) SOI CMOS logic was designed and implemented on a chip using a 0.5-
$\mu \text{m}$
CMOS test process. Radiation tests were conducted on the proposed logic chip to validate its SEE resistance to 50- and 25-MeV proton particles and its tolerance to TID effects for a total dose of 15-kGy(Si) gamma rays. The proposed SOI CMOS logic with the LMT can mitigate the atypical effects caused by radiation particles in semiconductor devices in radiation environments, such as space and nuclear power plants, thereby ensuring sufficient survival time under cumulative effects.