An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction

The neurons of spiking neural networks (SNNs) carry sparsity to the activation from temporal and spatial. To achieve high energy efficiency, this work proposes layer-wise configurable timesteps (LCTs) and channel-regrouped sparse convolution (CRSC) to explore and exploit the redundancy of temporal and spatial dimensions. In the temporal dimension, principal component analysis (PCA) is utilized to analyze redundant information in each layer, and LCT is adopted to balance and eliminate variable redundancies between layers. In the spatial dimension, channels are regrouped by spike activation frequencies to ensure workload balance, and sparse convolution is implemented to further accelerate SNN’s computation flow. A layer-fuse method that embeds the parameter of batch normalization in leaky integrate-and-fire (BLIF) is also proposed to reduce data movement and processing time. An energy-efficient SNN accelerator integrating the above methods is designed. Compared with the baseline, the hardware equipped with the proposed LCT can achieve
$3.22\times $
acceleration by redundancy elimination. The CRSC and BLIF can also reduce the hardware computation and memory access by
$3.24\times $
during inference. Implemented in TSMC 28 nm technology, this accelerator can achieve an energy efficiency of 36.89 TOPS/W at 650 MHz.