Dynamic RON Free 1.2-kV Vertical GaN JFET

Dynamic ON-resistance (
${R}_{\text {on}}{)}$
or threshold voltage (
${V}_{\text {TH}}{)}$
instability caused by charge trapping is one of the most crucial reliability concerns of some gallium nitride (GaN) high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic
${R} _{\text {ON}}$
and
${V}_{\text {TH}}$
stability of an industrial vertical GaN transistor-NexGen’s 1200-V/70-
$\text{m}\Omega $
fin-channel junction-gate field-effect transistor (JFET), fabricated on 100-mm bulk GaN substrates. A circuit setup is deployed for the in situ measurement of the dynamic
${R}_{\text {on}}$
under steady-state switching. The longer term stability of
${R}_{\text {on}}$
and
${V}_{\text {TH}}$
is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no
${R}_{\text {on}}$
or
${V}_{\text {TH}}$
shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field (
${E}$
-field) crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices toward power electronics applications.