Process and Simulation design of Silicon-On-Insulator (SOI) NMOS

As CMOS devices continue to shrink, traditional bulk-based MOSFETs are facing physical limits. In addition, the process compatibility of SOI and bulk has been confirmed. We develop an SOI-based NMOS technology to evaluate the scalability and use the Technology Computer Aided Design (TCAD) simulation software for verification. We find that the threshold voltage $(\mathrm{V}_{\mathrm{t}\mathrm{h}})$ of the SOI NMOS samples is over 0.5 V. In this paper, we introduce the SOI technology and discuss the calibration of $\mathrm{V}_{\mathrm{t}\mathrm{h}}$ in process simulation by doping phosphorus close to the oxide layer on the channel. First, we simulate the annealing rate to optimize the device characteristics, and then adjust the $\mathrm{V}_{\mathrm{t}\mathrm{h}}$ with the channel doping of phosphorus. The simulation results show that before the gate oxide layer is deposited, doping with appropriate phosphorus concentration and implantation energy can effectively control $\mathrm{V}_{\mathrm{t}\mathrm{h}}$ at 0.3 V, and achieve optimized subthreshold swing and maintain high $\mathrm{I}_{\mathrm{o}\mathrm{n}}/\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$ ratio at the same time, which can be applied to low-power ICs.