Low-Power Pattern Recognition System Using Spintronics Compute-in-memory Architecture

Pattern recognition plays an important role in image recognition, classification, and information processing. In this work, energy energy-efficient spintronics-based pattern recognition design using in-memory computing architecture is presented. The paper presents a faster, energy-efficient, and area-efficient pattern recognition approach with three computational steps per pixel recognition process using the training and mean image size. The reduction in critical switching current owing to the voltage-controlled switching mechanism results in a 43% reduction in power consumption as compared to all-spin logic-based design approach for recognizing a $3\times 3$ pixel image size pattern. This circuitry saves 33% area overhead when compared to conventional compute-in-memory (CiM) architectures based on spin orbit torque. The proposed CiM architectures can further be used for real-time pattern recognition for several applications.