Low Temperature Junction Formation for EZ-FET

The EZ-FET is a device with simplified architecture and processing that enables fast electrical characterization of semiconductor films on insulators (SOI) with only two lithography levels and using regular process steps. For low temperature SOI substrates characterization, the EZ-FET must be processed at a low temperature, including the junctions formation, i.e., the dopant activation process. Two EZ-FET dopant activation approaches using nanosecond laser annealing at low thermal budget are presented in this work. The first is the classical process of partial source and drain amorphization followed by their recrystallization. The second is a simplified process consisting of full source and drain amorphization followed by recrystallization. Both approaches are evaluated through the analysis of the electrical behaviors of the resulting structures.