A DfT Technique for Electrical Interconnect Testing of Circuit Boards with 3D Stacked SRAM ICs

A Design-for-test (DfT) technique is proposed in this paper for a test method, by which detecting open defects occurring interconnects between 3D stacked SRAM IC and a printed circuit board and among dies inside them. The test method is based on the supply current that is made flow through an interconnect to be tested. The DfT technique utilizes a built-in current sensor circuit to detect the open defects. It is shown that open defects occurring at interconnects among dies designed by the DfT method in a 3D stacked SRAM IC, and between the IC and a circuit board can be detected by the supply current test method.