Adaptive SAT Modeling for Optimal Pattern Retargeting in IEEE 1687 Networks

A wide variety of embedded instruments are increasingly integrated within modern System-on-Chips (SoCs) for the purpose of monitoring, debugging, and testing. Integrating this heterogeneous set of embedded instruments within the same chip necessitates having an efficient access network. Such a network should ensure minimal access time to the embedded instruments. The IJTAG standard was introduced as an efficient access methodology for instruments embedded in chips. The required configurations to access the desired instruments are generated in a process called pattern retargeting. For optimal retargeting, it is important to minimize the time taken to find the right configuration vectors as well as the time to access the desired instruments. In this work, we express the two execution times using the term Dynamic Access Time (DAT). This work proposes an adaptive retargeting model based on the Boolean Satisfiability Problem (SAT) that properly fits any arbitrary IJTAG network. The proposed model should provide substantial improvement, especially for runtime applications requiring dynamic retargeting, such as debugging operations. To assess the effectiveness of our proposed model, a comparison between state-of-the-art retargeting techniques and our work is performed. The results show an improvement in retargeting time of 60%, on average, compared to previous SAT-based retargeting approaches.