HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip

A digital signature is a cryptographic technique used to generate the signature of a message and verify the signature of that particular message. This signature scheme can ensure the validation of the authenticity, integrity, and non-repudiation of a message. Nowadays, the public-key cryptosystem RSA is widely used to perform the digital signature by using a public/private key pair. This paper describes the software and hardware hybrid implementation of the RSA digital signature on a System-on-Chip (SoC) that uses a RISC-V processor as processing core. The key generation for the RSA has been done in software, and the most time-consuming mathematical operation behind the RSA algorithm, the modular exponentiation, has been implemented in hardware. The proposed approach has been validated using one Xilinx Kintex-7 FPGA on the Genesys-2 FPGA board. The acceleration factor has also been calculated by comparing the software versus hardware implementation. The designed RSA IP has the flexibility to be reconfigured with different key sizes (512, 1024, 2048 bits) as per the requirements of the security level. The proposed implementation is verified using the National Institute of Standards and Technology (NIST) test vectors.