Performance Analysis of Ternary Full Adder designs using proposed Ternary 3:1 MUX

This paper proposes a novel circuit design of a Ternary Full Adder (TFA) using a proposed Ternary 3:1 multiplexer (3:1 TMUX) and proposed Ternary Half Adder (THA). This research focuses on achieving low power consumption and propagation latency in these proposed circuits. The proposed Ternary Full Adder circuit is compared with existing circuits and demonstrates superior performance based on their performance metrics. The circuit analysis and simulations were conducted using Cadence Virtuoso design environment at 90 nm technology. The simulation results indicate that the proposed designs outperform other existing circuits in terms of latency and power-delay product (PDP) and are suitable for high-performance Ternary computational circuits.