A New Fail Address Memory Architecture for Cost-Effective ATE

Memory test and repair has been generally applied to improve memory yield. However, due to the high cost of automatic test equipment (ATE) equipment, which has been employed for memory test and repair, there is a significant focus on reducing the ATE expense. One of the major problems, which contribute to the increase in ATE cost, is fail address memory. The size of fail address memory, where memory fault information is stored during the memory test, has continuously grown in line with the memory capacity increase. To address the problem, a new fail address memory architecture for cost-effective ATE is proposed in this article. In the proposed architecture, memory fault information is compressed and unrequired memory fault information is eliminated. In addition, a new structure of fail address memory is used to efficiently store memory fault information. Accordingly, the size of fail address memory is highly reduced in the proposed architecture. Furthermore, since some information, which can be used during the memory repair, can be collected during the memory test, the redundancy analysis time required to find memory repair solutions is also reduced in the proposed architecture. The advantages were verified experimentally.