Performance assessment of a new optimized Junctionless SiSn MOSFET

Junctionless Metal Oxide Semiconductor Field Effect Transistor (JL MOSFET) has attracted more consideration due to its simple fabrication process and improved performances. Moreover, this transistor is suitable for high scalability and low-power nanoelectronic applications. However, the low drift current (ON-state current) provided by this device and the degraded switching characteristics are the major issues that needs to be overcome. In this context, this work aims to propose a new design paradigm based on combined junctionless design and global metaheuristic optimization technique to improve the SiSn transistor performances for deep submicron microelectronic applications. It is demonstrated that the proposed design framework paves the way for the circuit designers not only to identify the appropriate materials for high drift current values, but also to realize high-performance transistors with high-speed commutation and low-power consumption, which are considered as important Figures-of-Merit (FoMs) for digital and analog integrated circuits applications. The developed approach based on combining the proposed junctionless structure with global metaheuristic optimization can open new paths for the design of high-performance and low-cost microelectronic devices.