SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation

We consider a method to measure the Single Event Upsets (SEU) sensitivity individually for PMOS and NMOS transistors. Using a circuit fabricated in a 65 nm bulk process, we performed α-particle irradiation. The SEU sensitivity of PMOS transistors is approximately 1/50 of that of NMOS transistors. Additionally, we investigated SEU rates by the drain area. The relationship between the area and SEU rates does not follow a linear function. We consider this phenomenon due to the proximity of the drain area to shallow trench isolation (STI), which prevents charge collection by a radiation strike.