Privacy by Memory Design: Visions and Open Problems

The threat to data privacy has never been more alarming than it is today. Among existing privacy-enhancing technologies, differential privacy (DP) is widely accepted as the de facto standard for privacy preservation. Yet, the software-based implementation of DP mechanisms is neither friendly for lightweight devices nor secure against side-channel attacks. In this article, we propose a first-of-its-kind design regime that realizes DP in hardware memories. The salient feature of this novel design lies in its transformation of the notorious memory noises at subnominal voltages into the desired DP noises, thereby achieving power savings and privacy preservation simultaneously: a “win-win” outcome. We demonstrate the feasibility of this design regime using a 1-Kb memory prototype based on 45-nm technology. For future prospects, a research road map that contains open research problems is delineated for the broad research community.