Nonlinearities of Multisampled Phase-Shifted PWM in Unbalanced Multicell Converters

This article reveals, analyzes, and proposes the method to mitigate nonlinear effects of multisampled multiupdate (MSMU) digital pulsewidth modulation (PS-DPWM) that appear in unbalanced multicell voltage-source converters (MC-VSCs). For balanced MC-VSCs, the harmonic cancellation of PS-DPWM allows for an increase in the sampling frequency, ensuring that the average current is acquired at the peaks, valleys, and intersections of all the triangular carriers. For unbalanced operation, which is typically encountered in practice, e.g., due to cell voltage mismatch in multilevel MC-VSCs and inductance mismatch in interleaved MC-VSCs, harmonic cancellation of PS-DPWM is compromised and, thus, the increased sampling frequency brings switching ripple in the feedback signal. Since in MSMU control the modulating signal is also updated at peaks, valleys, and intersections of all the carriers, this may cause vertical intersections between the modulating signal and the carriers, resulting in specific nonlinear effects. The nonlinearities are shown to introduce limit-cycle oscillations (LCOs) and output waveform distortion. A method to prevent such detrimental impact of MSMU-PS-PWM is also proposed. A simple analytical procedure is proposed to quantify the analyzed nonlinear effects, revealing that they are more emphasized for higher levels of imbalance and control bandwidth. Moreover, the modulator nonlinearity is shown to decrease as the number of cells increases. The analyses are verified in simulations and experiments, using laboratory prototypes of three- and four-level MC-VSCs.