A 1.6 GS/s 42.6-dB SNDR Synthesis Friendly Time-Interleaved SAR ADC Using Metastability Detection and Escape Acceleration Technique

This brief proposes a metastability detection and escape acceleration (MDEA) technique to enhance the bandwidth and lower the switching power of successive-approximation register (SAR) analog-to-digital converters (ADCs). It is implemented as an AC-coupling switched-capacitor latch (ACC-SCL) and applied to an 8-bit 4-channel time-interleaved SAR ADC, whose layout is synthesized automatically. The ADC has been fabricated in a 28-nm CMOS process, and the measurement results show that it achieves 1.6 GS/s, a 42.6-dB signal-to-noise-and-distortion ratio (SNDR) at Nyquist input, and dissipates 3.22 mW from 1.0 V power supply. The comparative experiments indicate that the MDEA technique reduces the switching power of the capacitor array from 1.20 mW to 0.95 mW, and improves the effective resolution bandwidth from 0.6 GHz to 0.8 GHz.