A Modeling and Simulation of ReRAM with Nonidealities for System-Level PIM Validation in System Verilog

This paper presents an efficient modeling approach of resistive random-access memory (ReRAM) for fast system-level validation of ReRAM-based processing-in-memory (PIM). The proposed of ReRAM model is implemented with XMODEL primitives in SystemVerilog, providing compatibility with Verilog models of PIM architecture. Various nonidealities of ReRAM are realized in the proposed model such as resistance states, switching voltages, and dynamic current fluctuation. Hence, ReRAM-based PIMs can be modeled and validated in more accurate and efficient way with the proposed ReRAM model. Compared with previous Verilog-A modeling approaches, the proposed modeling achieves about 95% simulation time reduction in 64 ReRAM cell array.