Single-Body-Integrated Complementary Tunneling Field-Effect Transistor (SBI CTFET) and Design Consideration of Processing Margin in Dual-Gate Formation

In this work, a novel single-body-integrated complementary tunneling field-effect transistor (SBI CTFET) is proposed and optimally designed by series of rigorous device simulations. The proposed device demonstrates both n-type and p-type enhancement operations free from the ambipolar characteristics of a TFET sharing the channel in common, enabling highly reliable operations and plausibly scaled cell area. The subthreshold swing (S) values for n-type and p-type in the single cell were 55 mV/dec. Moreover, the processing margin in forming its dual gates is systematically suggested for future designers.