Thermally-Aware Multi-Core Chiplet Stacking

Heterogeneous integration has enabled the interconnection of chiplets in 2.5D and 3D configurations within a package. Stacking a high-performance multi-core processor chip let on top of another is challenging due to hot spot exacerbation in the stack. Temperature-induced DVFS throttling defeats any potential performance gain that results from the shorter vertical connections in-between the on-chip interconnection networks in each chip let. We present and evaluate minimally-invasive floor-plan transformation techniques that space out chiplet hot spots away from each other in the 3D stack using layout mirroring and offsetting. Chiplet redesign efforts are reduced, and cycle times are preserved. The resulting thermally-aware multi-core chiplet stacking techniques reduce the peak temperatures and temperature-induced performance throttling compared to naive chiplet stacking. Empty offset areas are then used to extend the on-chip cache capacity for further performance improvement. The multi-core stacking techniques are illustrated on a 14 nm Intel Skylake-SP-like (server) floorplan model using a cycle-level multi-core CPU performance simulator incorporating power and thermal modeling components.