Impact of Process-Induced Inclined Sidewalls On Small Signal Parameters of Silicon Nanowire GAA MOSFET

In this work, calibrated TCAD simulation results are used to examine the impact of process-induced inclined sidewalls on small-signal parameters of the nanowire (NW) gate-all-around (GAA) MOSFETs. The non-quasi-static (NQS) small-signal instead of the quasi-static (QS), parameters are extracted for better accuracy at higher operating frequencies. The distributed channel resistances (Rgd and Rgs) and the intrinsic terminal capacitances (Cgd, and Cgs) are susceptible to the inclination of sidewalls angle ($\theta$). The increase in $\theta$ causes the distributed channel resistances to increase and the terminal capacitances to decrease.