Toward Reliability- and Variability-Aware Design-Technology Co-Optimization in Advanced Nodes: Defect Characterization, Industry-Friendly Modeling, and ML-Assisted Prediction

Reliability- and variability-aware design-technology co-optimization (RV-aware DTCO) becomes indispensable with advanced nodes. However, four key issues hinder its practical adoption: the lack of characterization technique that offers both accuracy and efficiency, the lack of defect model with long-term prediction capability, the lack of compact model compatible with most EDA platforms, and the low efficiency in circuit-level prediction to support frequent iterations during co-optimization. Demonstrating with 7-nm technology, this work tackles these issues by developing an efficient characterization method for separating defects, introducing a comprehensive test-data-verified defect-centric physical-based model and an industry-friendly open model interface (OMI)-based compact model, and proposing a machine learning (ML)-assisted approach to accelerate circuit-level prediction. With these achievements, an RV-aware DTCO flow is established and demonstrated on 3-nm gate-all-around (GAA) technology to bridge the material level to the circuit level. The work paves ways in boosting adoption of RV-aware DTCO in both circuit design and process development for ultimate nodes.