A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network

This paper proposes implementation-friendly cooperative spectrum-sensing (CSS) algorithm for the data fusion based cooperative cognitive-radio network. It has been designed with the notion of alleviating the computational complexity that results in efficient hardware design, without degrading the detection performance. In addition, this work presents hardware-efficient architecture of cooperative spectrum sensor (CSR), based on the suggested CSS algorithm and with the aid of resource-sharing architectural optimization. Extensive performance analysis of our CSS algorithm showed that the detection probability of 0.9 has been achieved at the signal-to-noise ratio (SNR) of −2.6 dB which is adequate for many real-world applications. Furthermore, hardware implementation of the proposed CSR architecture is carried out on the FPGA platform (Nexys-4 DDR Artix-VII board) and its functional validation is performed in real-world scenario. Subsequently, the suggested CSR is ASIC synthesized and post-layout simulated in UMC 90 nm-CMOS technology node. As a result, it occupies a silicon area of 0.0369 mm2 and it is capable of operating at a maximum operating frequency of 251 MHz. This design has a latency of 79 clock cycles and it delivers a sensing time of
$0.31 ~\mu \text{s}$
while operating at the aforementioned maximum clock-frequency. In comparison to the state-of-the-art implementation, the proposed CSR occupies 34.1% lesser area, delivers
$10\times $
shorter sensing time, and has achieved
$15.45\times $
better hardware efficiency.