NAND/NOR adiabatic gates: power consumption evaluation and comparison versus the fan-in

In this paper, adiabatic and conventional CMOS NAND/NOR gates are analytically compared at the gate level versus the fan-in. The comparison was carried out assuming both an assigned power supply and setting it to minimize power consumption. The analysis led to simple expressions, independent of the technology used which allow us to understand how the power advantage of adiabatic logic diminishes when the complexity of the implemented Boolean function is increased. The analytical results were validated by Spice simulations using both 0.8- and 0.35-/spl mu/m CMOS technology. The analysis shows that with the technologies considered for the nonoptimized design, the adiabatic style is advantageous at frequencies lower than about 30 MHz. This advantage is drastically reduced to frequencies below 1 MHz when there is a fan-in higher than five. These values are further reduced by a factor of eight in the case of optimized design. In this paper, technological trends together with a partially adiabatic style are also considered and discussed.