Body resistance model for Partially Depleted SOI device: charge-based approach, extraction and Verilog-A implementation

The Partially Depleted Silicon On Insulator (PDSOI) transistor is used for a wide range of applications, in particular for RF. The current standard compact model of SOI-like transistor does not take into account a bias dependence of the body resistance. Building upon our experience developing the PSP model, we propose here a stand-alone Verilog-A model of body resistance. This nonlinear resistance model is validated against 3D TCAD and 65nm PDSOI experimental data.