Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays

The recently developed logic-in-memory offers a high-performance and energy-efficient paradigm based on crossbar arrays of emerging non-volatile devices. However, the low resistance of magnetoresistive random-access memory (MRAM) results in significant power consumption in a conventional crossbar array, making it challenging to construct an efficient logic-in-memory. In this brief, we present a crossbar array of voltage-gated spin-orbit torque (SOT)-MRAM devices and establish a logic-in-memory scheme that implements majority gates in the crossbar arrays for reading operations. The multiple cells of the voltage-gated SOT-MRAM devices are connected in series, and each branch’s resistance is determined by adding the resistances of all the selected cells on it. In comparison to parallel connection schemes, the effective resistance
$({R_{eff}})$
in series connections are 25 times greater, resulting in lower read currents and improved energy efficiency. A case study of a 1-bit full adder serves as proof of the proposed logic-in-memory based on majority gates. These results indicate that the resistance summation in the voltage-gated SOT-MRAM crossbar arrays with majority gates is a preferred platform for logic-in-memory.