Polynomial Formal Verification of KFDD Circuits

As the complexity of digital circuits increases, their verification poses an increasingly difficult challenge. Simulation techniques cannot fully guarantee the correctness of a circuit and thus, formal verification techniques (such as BDDs or SAT) have to be used. However, their application can generally require exponential time and space. Consequently, the verification complexity of several circuits has been researched in recent years. Among other circuits, it has been proven that circuits derived from BDDs can be verified efficiently in polynomial time and space. However, for some functions, circuits derived from KFDDs have at most the same size and can even be exponentially smaller than BDD circuits. In this paper, we show that the verification complexity of KFDD circuits is linear and improve the previously proven upper bound for BDD circuits. The verification is carried out using KFDDs, where we give linear upper bounds for the KFDD size during the verification process, as well as for the overall time complexity. The theoretical results presented in this paper are supported by an experimental evaluation verifying several KFDD circuits.CCS CONCEPTS• Hardware $\rightarrow$ Functional verification.