Effects in Commercial p-Channel Power VDMOS Transistors Initiated by Negative Bias Temperature Stress and Irradiation

This paper investigates the impact of negative bias temperature stress on irradiated commercial p-channel power VDMOS transistors, particularly focusing on gate oxide charge and interface trap alterations and their contribution to threshold voltage shifts. The study addresses the critical issue of transistor reliability, as threshold voltage shifts can significantly affect device performance, especially in elevated temperature and negative gate oxide field conditions. Additionally, the research explores the effects of irradiation on VDMOS power transistors, emphasizing the importance of understanding the associated electrical parameter changes. The paper presents a comprehensive analysis of static and pulsed NBT stressing, with a specific focus on novel stress signals encountered in practical applications. The experimental procedure involves irradiation and NBT stress, and the results reveal insights into the contributions of gate oxide charge and interface traps to threshold voltage shifts. The findings shed light on the reliability of electronic equipment incorporating p-channel power VDMOS transistors under various stress conditions, offering valuable insights for device design and operation.