0.9-V sense-amplifier-based reduced-clock-swing MTCMOS flip-flops

Scaling-down V/sub DD/ as well as adopting a reduced-swing clock simultaneously is the key technique proposed in this work which results in remarkable power reduction for VLSI chips. Several configurations of 0.9-V MTCMOS (multi-threshold CMOS) flip-flops with reduced clock-swing (RCSFFs) are investigated in this work. By using the MVT technique, and the pulsed-low reduced-swing clock, the performance of the master stage of the new low-V/sub DD/ RCSFF is improved significantly. If the slave stage is constructed with the low-V/sub T/ SR latch, the new RCSFF is even 5% faster and 10% more power efficient than the low-V/sub DD/ full-clock-swing FF. If the slave stage is constructed with the MVT improved SR latch, the new RCSFF does not require a standby-controlled PMOS and is 18% faster than the low-V/sub DD/ RCSFF with a high well bias and 15% more power efficient than the low-V/sub DD/ full-clock-swing flip-flop.