A V-driver circuit for lowering power of sub-0.1/spl mu/m bus

A bus driver circuit which reduces the power dissipation of interconnects is described. The proposed V-driver prevents simultaneous signal transitions of opposite direction. Simulated results show up to 42.2% power reduction for 65 nm CMOS technology. A test chip was fabricated and measured. The results show a 10.7% power reduction at 100 MHz, 1.0 V operation.