A two-step A/D converter in digital CMOS processes

This paper describes a 3 V 8-bit 50 MSPS two-step analog-to-digital converter implemented in a 0.35 /spl mu/m 1P4M logic CMOS process. A PMOS biased in accumulation mode was used as a coupling capacitor in this ADC, so that the more expensive mixed mode process with double poly or MIM capacitors can be avoided. A modified switch box which greatly reduces the number of switches needed was also presented in this paper. The modified switch box can reduce the capacitance loading effect of the resistor ladder DAC (R-DAC) thus making the settling time of the DAC faster. The ADC occupies a die area of 0.38 mm/sup 2/ (450 /spl mu/m*850 /spl mu/m) and dissipates 64 mW at 50 MHz clock rate with 3 V single supply voltage. The FFT simulation result shows that the SNDR is 48.18 dB at 5 MHz input frequency and 50 MSPS conversion rate and the static simulation shows that the max. INL/DNL is less than 0.5 LSB/0.5 LSB.