A 5.5 GHz prescaler in 0.18 /spl mu/m CMOS technology

A high-speed dual-modulus divide-by-32/33 prescaler (DMP) has been fabricated in a standard 0.18 /spl mu/m CMOS process. It consists of a divide-by-4/5 synchronous divider implemented in MOS current-mode logic and a divide-by-8 asynchronous counter realized in differential cascode voltage-switch logic. A fully differential architecture is adopted, which offers immunity against noise, fabrication process and supply voltage variation. The measured operating frequency range is from 4.6 to 6.2 GHz, making it suitable for WLAN applications. Including the buffers, the circuit draws about 29 mA from a 1.8 V power supply and occupies less than 1 mm/sup 2/ die area.