Design and Analysis of Redistribution Layer Interposer Channel Considering Signal Integrity for High Bandwidth Memory Module

In this paper, we designed and analyzed redistribution layer (RDL) interposer channels for high bandwidth memory (HBM) module. The physical dimensions and material properties were designed based on recent RDL process technology. We analyzed the electrical performance of the RDL interposer channels in terms of insertion loss and far-end crosstalk (FEXT) with comparison to silicon interposer. To verify the performance of RDL interposer channels, eye diagram simulation was conducted based on the HBM3 setup conditions. Conventional RDL interposer show improved performance in terms of IL, but shows significant FEXT at high frequencies. From eye diagram of interposer channels, RDL show high eye distortion due to the composite effect of crosstalk and voltage ringing. As a future projection, RDL interposer was designed and analyzed considering the rise in maturity of RDL based process. As a result, we have shown that with future advances in RDL fabrication technology, RDL interposer channels can successfully be utilized for HBM3 applications at a data rate of 6.4 Gb/s.