CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs

Convolutional neural networks (CNNs) are quickly becoming one of the most common applications running on hardware accelerators. Considering field programmable gate arrays (FPGAs), due to their high flexibility and computational performance, they are suitable for fast classification tasks and therefore, pave the way for new machine learning inference approaches. In this work, we first designed a fully interconnected CNN architecture implementable on a single FPGA. Second, we developed a new neural node-oriented placement algorithm to enable resilient CNN accelerators on space-grade FPGAs. The proposed solution reduces the single event transient error sensitivity of CNN single neuron cores while achieving high performance and effective overall convolutional architecture fault tolerance. The developed approach has been applied and integrated into a state-of-the-art radiation tolerant FPGAs (RTG4) implementation flow. The experimental evaluation has been performed on a microchip test board through benchmark application performance evaluation and transient error analysis. Experimental results demonstrate an improvement of 27.2% of the maximal working frequency and a reduction of the transient error sensitivity of about three times with respect to the previous mitigation approaches.