Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks

Nanometer circuits are becoming increasingly susceptible to soft errors. Selective hardening is a less expensive technique to improve the reliability of circuits because it hardens the critical components instead of hardening an entire circuit. One challenge of selective hardening is efficiently and effectively identifying the critical parts in circuits. Simulation-based fault injection is commonly used but extremely time-consuming, especially for complex circuits. This article proposes an approach based on graph neural networks (GNNs) to identify critical flip-flops in circuits. GNNs can take advantage of the circuit’s structural features and the features of individual flip-flops. To convert the features into abstract data that can be fed into GNNs, we provide a feature extraction method that uses a graph model to represent the relevant features of the circuit. The method converts the target circuit into a graph representing its architecture. The graph also contains features of individual flip-flops extracted from the circuit’s netlist and the value change dump (VCD) waveforms of the test used for fault simulation. Additionally, we extract edge features in the graph to utilize the information on combinational gates on the path between flip-flops. Datasets generated based on two open-source RISC-V cores are used to validate the proposed approach. We compare the performance of different GNNs on them and discuss the contribution of edge features to their performance. Our experiments show that the prediction accuracy increases significantly with edge features. GraphSAGE and SAGE-GCN with edge features perform best among the selected GNNs. The highest accuracy we achieved on Ibex and RI5CY is 97.75% and 98.67%, respectively. We also provide a method to accelerate the process of critical flip-flop identification.