8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips

Efforts to advance the use of analog SRAM compute-in-memory (SRAM-CIM) macros for high-precision multiply-and-accumulate (MAC) operations must deal with issues pertaining to energy efficiency, computing latency (TAC), and area overhead. This brief presents a novel SRAM-CIM structure that utilizes (1) a high input precision computing cell (HIPCC) to perform 8b-MAC operations with high multiplication throughput, and (2) a global bitline-combining (GBL-comb) scheme to improve energy efficiency by reducing the number of analog-to-digital converters (ADCs). A 28nm 384-kb SRAM-CIM macro with 20-bit output precision (near-full precision) was fabricated using a foundry-provided 28nm logic process for MAC operations with 8b-input, 8b-weight, and 16 accumulations. The resulting macro achieved a
$T_{\mathrm{ AC}}$
of 3.6 ns with energy efficiency of 14.97 TOPS/W when applied to 8-bit MAC operations.