A Highly Efficient QEC Decoder Implemented on FPGA and ASIC

To make quantum computers useful and run applications featuring trillions of reliable logical operations, error correction will be required. One of the key components to enable error correction is a decoder that can identify errors which accumulate during the execution of a quantum circuit. The requirements for a decoder are that it accurately detects errors, executes quickly enough as to not create a backlog, and has low power usage so it can scale to millions of qubits and be more easily co-located with the wider qubit control apparatus. In this paper we present a decoder which for a distance 23 rotated planar surface code with 0.1% circuit-level depolarising noise executes in 240ns per round, has a threshold of 0.78%, occupies 0.06mm2 on a CMOS based silicon chip, and consumes less than 8mW of power.