Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis

The susceptibility of Integrated Circuits (ICs) to soft errors has always been a major concern. However, the shrinking of CMOS technology nodes, which results in high frequency, low power, and small area, exacerbates the problem of radiation-induced soft errors. The significance of accurately evaluating the ICs’ vulnerability to such errors should not be disregarded, especially when a radiation-hardening process is developed. To this end, the dynamic consideration of Single Event Transient (SET) propagation may provide more accurate results compared to related works. In this paper, we present a gate-level event-driven Soft Error Rate (SER) estimation framework that models the generated SETs as event pairs that propagate through the circuit. Dynamic Timing Analysis (DTA) is performed to specify the arrival time of the SETs at flip-flop inputs and detect a soft error. Experimental results indicate that our event-driven approach leads to 14.96% more accurate SER estimation over conventional graph-based techniques, with respect to SPICE simulation.