An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing

For VLSIs which are built in mission-critical systems, field testing is required to detect defects caused by aging degradation. However, it is a difficult problem to comprehensively test circuits in a short time such as time for power on / off. To solve this problem, we propose a non-scan based built-in self-test method using a status signal sequence which executes all k-consecutive state transitions in controllers n times. In this paper, we propose structural symbolic simulation using control signal sequences generated from the status signal sequences and the structure of data-paths at register transfer level. We evaluate the estimated field random testability for hardware elements in data- paths using the structural symbolic simulation and analyze the relationship with the fault coverage at gate level and the estimated field random testability at register transfer level.